1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory with a sidewall control gate structure in which a single cell is written by applying the same high voltage pulse to two adjacent control gate lines in a cell array.
2. Description of the Related Art
Conventionally, a NAND flash EEPROM is known as an electrically erasable and highly-integrated nonvolatile semiconductor memory. A NAND flash EEPROM memory transistor, as shown in FIG. 1, has a stacked gate structure where diffusion layer regions 18, which become a source region or a drain region in a semiconductor substrate 26, are formed, and a control gate 2 and an electric charge accumulation layer, which is configured from a floating gate 8, are further stacked on the semiconductor substrate 26 via a first gate insulating film 30, which becomes a tunnel insulating film. A NAND memory cell unit is configured by connecting a plurality of memory transistors in series as shaped columns such that neighboring memory cell transistors share either a common source or a common drain region, and arranging select gate transistors at both sides of the columns of memory cell transistors. In FIG. 1, given that Cono denotes a capacitor between the control gate 2 and the floating gate 8, and Cox denotes a capacitor between the floating gate and the semiconductor substrate 26, when a control gate voltage Vcg is applied to the control gate 2, a voltage Vfg for the floating gate 8 is determined through capacitive coupling of Cono and Cox and is represented by the following equations:Vfg=Cr×(Vcg−Vt+Vt0)  (1)Cr=Cono/(Cono+Cox)  (2)where, Vt denotes a threshold voltage of memory cell transistors, and Vt0 denotes a threshold voltage (intermediate threshold voltage) when there are no electric charges in the floating gate 8.
Problems of a conventional memory cell transistor structure shown in FIG. 1 are described below. The greater the voltage Vfg for the floating gate 8, the higher the voltage applied to the tunnel insulating film 30, and electron injection into the floating gate 8 easily occurs. It can be understood from Equation (1) that when voltage Vcg to be applied to the control gate 2 is a constant, capacity ratio Cr in Equation (2) should be large in order to increase the floating gate voltage Vfg. In other words, a greater Cono is needed relative to Cox in order to lower the write-in voltage. For example, increasing the capacitance between a booster plate and the floating gate allows development of a NAND EEPROM that is writable/erasable/readable with a low voltage (Japanese Patent Application Laid-open No. Hei 11-145429). In addition, increasing the coupling ratio of the floating gate to the control gate so as to decrease the write-in voltage allows development of a miniaturized nonvolatile memory (Japanese Patent Application Laid-open No. 2002-217318). A nonvolatile semiconductor memory using MOSFETs as memory elements, each having a floating gate on both sidewalls of the control gate and thereby improving write-in, erasure and read-out characteristics, has been developed (Japanese Patent Application Laid-open No. 2002-50703). Also, an AG-AND memory, which has an assisting gate arranged close to the floating gate, has been developed (Y. Sasago, et. al, “10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology”, Technical Digests of International Electron Devices Meeting, 2002 IEEE, 21.6.1, p. 952–954).
A memory cell array is configured by arranging NAND memory cell units in a matrix. NAND cell units arranged in a row are called a ‘NAND cell block’. The gates of select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of memory transistors arranged in the same row are connected to the same control gate line. When N memory transistors are connected in series in a NAND memory cell unit, N control gate lines are included in a single ‘NAND cell block’.
The memory transistor nonvolatilely stores data defined by the charge accumulation state of the floating gate. Specifically, binary data storage is performed with, for example, higher voltages resulting from injecting electrons into a floating gate through a channel, than with a certain threshold voltage as data ‘0’ and lower voltages resulting from discharging the electrons stored in the floating gate through the same channel as data ‘1’. Recently, a multilevel-valued storage method such as 4-valued storage has also been implemented by finer control of the threshold distribution.
When performing data write-in, the entire data stored in the NAND cell block is erased all at once. This is performed by setting all control gate lines (word lines) of the selected NAND cell block to a low voltage Vss (for example, 0V), applying a high positive voltage Vera (erasure voltage, for example, 20V) to a p-well 26 containing the cell array, and discharging the floating gate electrons to the channel. Accordingly, all the data in the NAND cell block becomes data ‘1’. Not only can a NAND cell block be erased all at once, but so can an entire chip.
Writing data is performed all at once after the collective data erasure described above for a plurality of memory cell transistors connected to the selected control gate lines. The write-in unit is normally defined as one page; however recently, there are cases where a plurality of pages are allotted to a single control gate. The write-in order for the control gate lines in the NAND cell block may be an arbitrary order (random write-in) or an order in a certain single direction (sequential write-in). Sequential write-in is normally performed, in order, from the control gate line on the source side.
Applying a high positive voltage Vpgm (a write-in voltage, for example, 20V) to the selected control gate line so as to write in control gate lines all at once allows execution of two types of simultaneous data write-in: in the case of data ‘0’, electrons are injected from the channel to the floating gate 8 (namely, ‘0’ write-in), and in the case of data ‘1’, electron injection is restricted (namely, write-restricted, or ‘1’ write-in). Implementing such control gate line collective write-in requires controlling the channel voltage for the memory cell transistor, depending on data. For example, in the case of data ‘0’, the channel voltage is kept low, and when a write-in voltage Vpgm is applied to the control gate 2, a corresponding large electric field is impressed on the gate insulating film 30 below the floating gate 8. On the other hand, in the case of data ‘1’, electron injection to the floating gate 8 is restricted by boosting the channel voltage and decreasing the electric field that is impressed on the gate insulating film 30. At this time, if the boost in the channel voltage is insufficient, electron injection occurs and the threshold then fluctuates even with a ‘1’ write-in memory transistor. This phenomenon is hereafter called ‘erroneous write-in’. Implementing the write-in operation for a NAND flash EEPROM requires controlling the threshold fluctuation, due to an erroneous write-in, within the specified limits within which misoperations do not occur.
As methods for channel voltage control during write-in, a self-boosting (SB) write-in method (K. D. Suh, et. al, “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30. NO. 11, NOVEMBER 1995, p. 1149–1156), and a local self-boosting (LSB) method (Japanese Patent Application Laid-open No. Hei 8-279297) are known. In addition, an erasure area self-boosting (EASB) method has been proposed (Japanese Patent Application Laid-open No. Hei 10-283788). On the other hand, as a method of improving initial charging voltage, a channel voltage boosting method has been proposed, which increases the initial voltage by transferring a bit line voltage without decreasing below the threshold through temporarily boosting the voltage for the bit line (first end) side select gate line during initial voltage transfer (Japanese Patent Application Laid-open No. Hei 10-223866).
There are two types of stress that cause ‘erroneous write-in’: ‘Vpgm stress’ and ‘Vpass stress’. The write-in restriction (‘1’ write-in) for unselected memory cell transistors, which are connected to a selected control gate line and to which a write-in voltage Vpgm is applied, is performed by boosting the channel voltage for the unselected memory cell transistors through capacitive coupling with one or a plurality of unselected control gate lines. An intermediate voltage Vpass is applied to all or a part of the unselected control gate lines for boosting the channel voltage. However, an erroneous write-in occurs if the intermediate voltage Vpass is too small. This stress applied to the unselected memory cell transistors is called ‘Vpgm stress’.
On the other hand, since the channel voltage for the unselected memory cell transistors in the NAND cell unit to which ‘0’ write-in is to be performed is small, erroneous write-in occurs if the aforementioned intermediate voltage Vpass is too large. This stress applied to the unselected memory cell transistors is called ‘Vpass stress’.
There are two types of write-in order for the control gate lines in the NAND cell block: a random write-in method of writing in an arbitrary order regardless of control gate line location, and a sequential write-in method of writing in order from, for example, the source line SL side control gate line. Recently, however, there is a tendency to use the latter sequential write-in method. In the case of the sequential write-in method, all of the selected memory cell transistors and the unselected memory cell transistors closer to the bit line BL side are in an erased state, which greatly influences the erroneous write-in characteristics.
In order to reduce the Vpgm stress, several channel voltage control methods have been proposed. The conventional methods have been proposed from the perspective of how to increase the efficiency in boosting the channel voltage; however, these attempts are reaching a limitation, and improving boost efficiency is becoming difficult.
In a conventional NAND flash EEPROM, the intermediate voltage Vpass, which is an intermediate voltage between a cut-off voltage Vcutoff (=0V) and a high write-in voltage Vpgm, is applied to boost the diffusion layer regions 18 of memory cell transistors during ‘1’ write-in. Write-in characteristics for cells to which ‘1’ write-in is to be performed improve as the intermediate voltage Vpass for boosting the diffusion layer regions 18 increases. However, when considering ‘0’ write-in, since the voltage to be applied to cells other than the write-in cells in the NAND cell increases by increasing the intermediate voltage Vpass, a defect occurs where a cell to which ‘1’ write-in has already been performed changes as if a ‘0’ write-in was performed. Boosting the diffusion layer regions 18 necessary for ‘1’ write-in while lowering the value of the intermediate voltage Vpass is preferable.